1. Field of the Invention
The present invention relates to a general-purpose logic module and a cell using the same. More particularly, the present invention relates to a basic circuit configuration of the general-purpose logic module and a structure of the cell.
2. Description of the Related Art
Conventionally, a general-purpose logic module used in a typical field programmable gate array (FPGA) and a mask programmable gate array with a function block base have been well known. This general-purpose logic module is formed such that a designer can select one of a plurality of logic functions.
As a general-purpose logic module provided with a multiplexer in which a plurality of combination logic functions can be selected, for example, Japanese Laid Open Patent Application (JP-A-Heisei, 7-106949) corresponding to U.S. Pat. No. 5,055,718 entitled “LOGIC MODULE WITH CONFIGURABLE COMBINATIONAL AND SEQUENTIAL BLOCKS” discloses “General Purpose Combination Logic Module”. The general-purpose logic module disclosed in this gazette, as shown in FIG. 1, is provided with a four-input multiplexer (MUX). This four-input multiplexer is constituted by combining three two-input multiplexers.
This gazette does not clarify the configuration of the two-input multiplexer. Typically, a two-input multiplexer of a non-inversion output type is composed of inverters of a first stage, transfer gates of a second gate and an inverter of a third stage, as shown in FIG. 2. Thus, the inputted signal is passed through the logic elements of the three stages until the signal is outputted. If the four-input multiplexer shown in FIG. 1 is formed by using the two-input multiplexer having such configuration, the inputted signal is passed through the logic elements of six stages until the signal is outputted.
It should be noted that, when the two-input multiplexer is an inversion output type, the inverter of the third stage is removed. Thus, if the two-input multiplexer of this inversion output type is used to configure the four-input multiplexer shown in FIG. 1, the inputted signal is passed through the logic elements of four stages until the signal is outputted.
Moreover, the four-input multiplexer can be formed by using inverters and transfer gates as shown in FIG. 3, without any usage of the two-input multiplexer shown in FIG. 2. In the case of this four-input multiplexer shown in FIG. 3, the inputted signal is passed through the logic elements of four stages until the signal is outputted.
Also, as another general-purpose logic module, U.S. Pat. No. 5,684,412 discloses “CELL FORMING PART OF A COUSTOMIZABLE ARRAY”. This general-purpose logic module is composed of a NAND gate, two two-input multiplexers A, A, and one two-input multiplexer LARGE, as shown in FIG. 4A. The two-input multiplexer A is composed of inverters of a first stage and transfer gates of a second stage, as shown in FIG. 4B. The two-input multiplexer LARGE is composed of transfer gates of a first gate and an inverter of a second stage, as shown in FIG. 4C. Thus, the signal inputted to the general-purpose logic module shown in FIG. 4A is outputted after passed through the logic elements composed of a maximum of four stages.
In addition to the above-mentioned general-purpose logic modules, a general-purpose logic module provided with a multiplexer in which a plurality of combination logic functions can be selected is disclosed in U.S. Pat. Nos. 4,910,417, 6,014,038 and the like.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-223902) discloses “Semiconductor Integrated Circuit Apparatus”. This semiconductor integrated circuit apparatus is provided with: a first region and a second region which are formed on an SOI substrate and arranged in parallel to and independently of each other; a first MOS transistor of a first channel type and a second MOS transistor of a second channel type in which they are formed on the first region, and their source diffusion layer regions and drain diffusion layers are connected to each other through a first diffusion layer wiring; and a third MOS transistor of the first channel type in which it is formed on the second region, and its source diffusion layer is connected to a source diffusion layer of the second MOS transistor, or its drain diffusion layer is connected to a drain diffusion layer of the second MOS transistor through a second diffusion layer wiring.
Because of the above-mentioned configuration, it is possible to solve such conventional problems that a PN element separation region for arranging the bulk CMOS transistor is required, the connection using a metallic wiring is required to connect between the drain diffusion layers of an N-channel MOS transistor and a P-channel MOS transistor, and a wiring area within a block is increased.
Each of the above-mentioned general-purpose logic modules is provided with the multiplexer composed of the plurality of inputs and the plurality of stages, in which the plurality of two-input multiplexers are connected in serial at the plurality of stages. The desirable logic circuit is established by setting its input terminal to a logic value “1” (for example, a power supply potential) or a logic value “0” (for example, a ground potential).
However, the above-mentioned conventional general-purpose logic modules are formed such that the two-input multiplexers are connected in serial at the plurality of stages. Thus, the number of the stages of the logic elements through which the signal is passed becomes large. Moreover, the transfer gates are inserted in serial at the plurality of stages. For this reason, the conventional general-purpose logic modules have the defect that a switching speed is slow, as compared with a configuration of a circuit, such as a gate array cell base IC or the like, which can be provided with a simple logic circuit.
Its difference is extreme if the comparison is done between the function of a two-input NAND, a two-input NOR, a two-input EXOR, a two-input EXNOR and the like which are constituted by using the general-purpose logic module shown in FIG. 1 or FIG. 4A and the function of those which are constituted by using the gate array cell base IC or the like. Especially, in a case of a configuration using a usual ASIC, the difference of an inner gate delay characteristic occurring in the two-input NAND, the two-input NOR and the like that can be constituted by one stage logic is evident.
These problems are brought about because of a large number of logic element stages since the circuit configuration using the multiplexers composed of the plurality of inputs and the plurality of stages are employed such as the serial connection of the plurality of two-input multiplexers and because of the configuration of the logic circuit in which the plurality of transfer gates are inserted in serial.